The Three Buses - Data Highways
Part of CPU Architecture · GCSE GCSE Computer Science revision
This key facts covers The Three Buses - Data Highways within CPU Architecture for GCSE Computer Science. Revise CPU Architecture in 3.4 Computer Systems for GCSE Computer Science with 16 exam-style questions and 12 flashcards. This topic appears regularly enough that it should still be part of a steady revision cycle. It is section 5 of 8 in this topic. Use this key facts to connect the idea to the wider topic before moving on to questions and flashcards.
Topic position
Section 5 of 8
Practice
16 questions
Recall
12 flashcards
The Three Buses - Data Highways
Buses are the communication pathways connecting CPU components to memory and peripherals:
- Address Bus (one-way) - Carries the memory ADDRESS (WHERE to look). Like a postcode telling the postman which house. Goes FROM CPU TO memory only.
- Data Bus (two-way) - Carries the actual DATA (WHAT is being transferred). Like the actual letter being delivered. Goes both ways between CPU and memory.
- Control Bus (two-way) - Carries COMMAND signals (read, write, clock). Like instructions telling the postman what to do. Coordinates everything.
Address = WHERE (like an address on an envelope)
Data = WHAT (the actual content)
Control = HOW (read? write? when?)
Keep building this topic
Read this section alongside the surrounding pages in CPU Architecture. That gives you the full topic sequence instead of a single isolated revision point.
Practice Questions for CPU Architecture
Which component of the CPU carries out arithmetic and logical operations?
Name three main components of the CPU and state the purpose of each.
Quick Recall Flashcards
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