The Three Buses - Data Highways
Part of CPU Architecture — GCSE Computer Science
This key facts covers The Three Buses - Data Highways within CPU Architecture for GCSE Computer Science. Revise CPU Architecture in Systems Architecture for GCSE Computer Science with 15 exam-style questions and 12 flashcards. This is a high-frequency topic, so it is worth revising until the explanation feels precise and repeatable. It is section 5 of 7 in this topic. Use this key facts to connect the idea to the wider topic before moving on to questions and flashcards.
Topic position
Section 5 of 7
Practice
15 questions
Recall
12 flashcards
The Three Buses - Data Highways
Buses are the communication pathways connecting CPU components to memory and peripherals:
- Address Bus (one-way) - Carries the memory ADDRESS (WHERE to look). Like a postcode telling the postman which house. Goes FROM CPU TO memory only.
- Data Bus (two-way) - Carries the actual DATA (WHAT is being transferred). Like the actual letter being delivered. Goes both ways between CPU and memory.
- Control Bus (two-way) - Carries COMMAND signals (read, write, clock). Like instructions telling the postman what to do. Coordinates everything.
Address = WHERE (like an address on an envelope)
Data = WHAT (the actual content)
Control = HOW (read? write? when?)